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Microchip Technology /ATSAMV70N19 /SPI0 /MR

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Interpret as MR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (MSTR)MSTR 0 (PS)PS 0 (PCSDEC)PCSDEC 0 (MODFDIS)MODFDIS 0 (WDRBT)WDRBT 0 (LLB)LLB 0PCS0DLYBCS

Description

Mode Register

Fields

MSTR

Master/Slave Mode
PS

Peripheral Select
PCSDEC

Chip Select Decode
MODFDIS

Mode Fault Detection
WDRBT

Wait Data Read Before Transfer
LLB

Local Loopback Enable
PCS

Peripheral Chip Select
DLYBCS

Delay Between Chip Selects

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data